Typical high resolution video and videographic displays are based on CRT technology. Such displays require the provision of a serial data stream at a rate essentially matching the horizontal sweep speed of the CRT electron beam to provide the desired horizontal pixel display density. Current graphic video displays are typically providing display resolutions of 1280 (horizontal) by 1024 (vertical) pixel densities. Accordingly, for a display refresh rate of 30 frames per second, a maximum pixel update period of 25 nanoseconds must be supported. However, given the presence of frame margins and the requirement for beam retrace, each pixel refresh period is typically closer to 10 nanoseconds. Naturally, as display resolution increases, the pixel refresh period correspondingly diminishes.
Additionally, with increasing resolution of the video display, the corresponding video memory requirements will also increase. For a 1280 by 1024 video display resolution, a multiple bit per pixel video memory is often at least 160 k byte. Given considerations such as the use of multiple bits per pixel to support color and other video attributes and the use of a video memory field several times larger than the actual video display, video memory requirements of several megabytes are typical.
Another constraint on the management of video memories is the quite limited period available for video memory updating. That is, the only time available for altering the contents of the video memory field is during the electron beam retrace period which is typically only about ten percent of real time. Any video memory updating that occurs during the remaining 90% of real time ordinarily conflicts with the transfer of data from the memory field to the display via the electron beam. Such conflicts typically result in the occurrence of a visibly perceptible flicker of the display. However, limiting the update of the video memory field to only the retrace period greatly limits the rate at which the video memory field can be updated.
Consequently, various schemes for providing extended memory field update periods while meeting the necessary pixel refresh period requirements without incurring undesirable video effects have been proposed and implemented. One such solution is to provide an alternate video memory field, or alternate video memory page. Control circuitry associated with the two video pages allows one page to be always available for supporting the video display while the second page is available for video memory field updating. The two pages may then be simply swapped during the retrace period of the video display. Disadvantages of this approach include the complete doubling of the required video memory field size and the lack of any provision to enhance the video memory field access speed for pixel updates. Relative to both of these disadvantages is the fact that with increasing display resolutions this two page approach has an increasing requirement for high speed memory that is naturally of similarly increasing cost.
Another approach is to utilize a high speed serial shift register in conjunction with a simple video memory field. This approach utilizes successive parallel shifts of data to fill the serial shift register with each parallel shifted line of data corresponding to a line of a video memory field portion to be displayed. Serially clocking the data out of the serial shift register supports the serial stream requirements of the display while substantially increasing the amount of the display frame period available for updating the video memory field. Further, the serial shift register may be optimized for serial shift speed and, thereby, meet the required maximum pixel update period dictated by the video display horizontal resolution. The disadvantages of this approach generally surface when the display memory field, or at least a portion thereof, is implemented along with the serial shift register in a single chip architecture. In particular, the disadvantages include the requirement that each and every segment of the serial shift register be operational and, further, operable at a minimum shift speed sufficient to support at least the maximum pixel refresh period of the video display. However, utilization of redundant shift register segments is typically ineffective, i.e., replacement segment routing introduces significant serial shift delays. Additionally, the dedicated, sequential nature of the serial shift register also imposes a severe constraint on the implementation of any redundancy scheme for the accompanying on-chip portion of the video memory field. Another disadvantage is that in the optimization of the serial shift register for speed, the power requirements of the shift register circuitry are significantly increased. As such, the extent and complexity of the remaining on-chip circuitry is correspondingly reduced.